International Islamic University Chittagong (IIUC)
Compiled Midterm Exam Analyzer (Spring 2023 - Spring 2026)
Computer Architecture (CCE-3509) Question Analyzer
Comprehensive question bank and high-yield topic analyzer curated from Spring 2023, Spring 2024, Spring 2025, Autumn 2025, and Spring 2026 midterm papers. Filtered by semester years, marks, Bloom's taxonomy levels, and frequency of repetition.
5 Semesters
Analyzed Papers
4 Modules
Syllabus Breakdown
High-Yield
Repeated Tagging
30 Marks
Standard Exam Format
Module 1
Foundational Concepts
Basics of Computer Architecture & Organization
1. Computer Architecture vs. Computer Organization & Harvard vs. Von Neumann
Repeated (High Yield)
Spring 2026
Q1.a (4 Marks) [CLO1, R]: Distinguish between Computer Architecture and Computer Organization.
Autumn 2025
Q1.b (5 Marks) [CLO1, R]: Distinguish between Harvard Architecture and Von Neumann Architecture.
Spring 2025
Q1.a (4 Marks) [CLO1, U]: Explain the basic structure of a computer system including its main components.
Spring 2024
Q1.a (4 Marks) [CLO1, An]: Explain the contrast between computer architecture and computer organization.
Spring 2023
Q1.a (Marks not fully visible) [CLO1, An]: Differentiate between computer architecture and computer organization.
2. Evolution, Stored Program Concept, & Basic CPU Structure
Conceptual
Spring 2026
Q1.b (6 Marks) [CLO1, An]: Briefly discuss the evolution of computers and how these changes impacted computer performance and usability.
Autumn 2025
Q1.a (5 Marks) [CLO1, An]: Explain the basic architecture of a computer system including its main components.
Spring 2025
Q1.b & c (6 Marks) [CLO1, U/R]: Describe the difference between arithmetic and logic operations with examples. Define the term "Central Processing Unit (CPU)" and list its major parts.
Spring 2023
Q1.b (Marks not visible) [CLO1, R/U]: What is meant by the "stored program" concept? Draw a diagram of Von Neumann's architecture and explain it briefly.
3. Buses, Registers, and Hardware Interaction
Repeated (High Yield)
Autumn 2025
Q3.c (3 Marks) [CLO1, R]: What is BUS? Shortly explain the types of buses used in computer architecture.
Spring 2025
Q2.a (5 Marks) [CLO1, U]: Explain the role of buses in a computer system (data bus, address bus, control bus). How do they contribute to processor-hardware interaction?
Spring 2024
Q2.a & b (10 Marks) [CLO1, U/An]: Significance of address bus in 8085 µP vs data bus. Draw neat diagram and explain function of program counter (PC) register in a common bus system.
Module 2
High Frequency
Memory Hierarchy, Cache Memory, & Virtual Memory
1. Memory Hierarchy & Access Speed-Cost Trade-offs
Repeated (High Yield)
Autumn 2025
Q3.a (5 Marks) [CLO2, R]: What is memory hierarchy in computer architecture? Explain the significance of it.
Spring 2025
Q3.a (4 Marks) [CLO1, U]: What is the memory hierarchy in computer architecture? Explain its importance in terms of access speed and cost.
Spring 2024 / 2023
Q3.a / Q2 (4 Marks) [CLO2, U]: Explain hierarchical memory system access times/sizes, selection factors, and hierarchical importance diagrams.
2. Cache Memory, Pentium-4 Organization, & Cache Mapping Numericals
Repeated (High Yield)
Spring 2026
Q2.b (6 Marks) [CLO3, An]: Explain the role of cache memory in computer system. Illustrate cache organization of Pentium-4.
Autumn 2025
Q2.b (6 Marks) [CLO2, An]: How does the cache memory work in a computer system? Briefly describe Pentium-4 cache organization.
Spring 2025
Q3.b (6 Marks) [CLO2, Ap]: Cache hit, miss, fetching mechanism, and complete example explanation.
Spring 2024
Q3.b (6 Marks) [CLO2, An]: Numerical problems on Direct Mapped Cache & 4-way Set Associative Cache (TAG, OFFSET, INDEX calculations).
3. Virtual Memory & Short Notes
Short Notes
Spring 2026
Q3.a (4 Marks) [CLO1, R]: What is virtual memory? Highlight different types of virtual memory. Short notes: Cache replacement policy, DRAM, Thunderbolt, Volatile Memory.
Autumn 2025
Q3.a (2 Marks) [CLO1, R]: Short notes on Solid State Drive, Thunderbolt, Interrupt, and Register.
Module 3
Parallel Processing
Multiprocessors & Parallel Organization
1. Multiprocessor Systems & SMP vs. Distributed Architecture
Repeated (High Yield)
Spring 2026
Q2.a (4 Marks) [CLO1, U]: Define Multiprocessor. Explain characteristics of multiprocessors connected by a network.
Autumn 2025
Q2.a (4 Marks) [CLO1, U]: What is a multiprocessor system? Explain differences between symmetric and asymmetric multiprocessor.
Spring 2025
Q3.a & b (10 Marks) [CLO1/2, U/Ap]: Symmetric vs distributed architectures, 4-processor SMP block diagram design, task and resource sharing analysis.
2. SIMD Architecture & Serial vs. Parallel Communication
Architectural Design
Spring 2025
Q2.b (5 Marks) [CLO2, Ap]: Explain why modern systems prefer serial communication over parallel despite slower theoretical data rate.
Spring 2024 / 2023
Q1.b / Q2.b (6 Marks) [CLO1/2, U]: What is a SIMD computer? Explain architecture using block diagram and identify suitable applications.
Module 4
I/O Systems
Input/Output Organization & Interrupts
1. Direct Memory Access (DMA)
Repeated (High Yield)
Spring 2026
Q3.b (6 Marks) [CLO2, An]: Demonstrate working procedure of Direct Memory Access (DMA) on a computer system. Advantages.
Spring 2025
Q3.b (5 Marks) [CLO2, An]: Explain working principles of Direct Memory Access (DMA) on a computer system and its advantages.
Spring 2023
Q2.b (Marks visible) [CLO1, E]: Explain working of DMA using suitable block diagram with an example application.
2. Programmed I/O & Interrupt-Driven I/O
I/O Methods
Autumn 2025
Q3.b (5 Marks) [CLO2, U]: Define Programmed I/O. Discuss different types of commands in Programmed I/O.
Spring 2026
Q3.b (6 Marks) [CLO2, An]: Define Interrupt driven I/O. Analyse how it uses interrupt signal to improve CPU efficiency.
Spring 2023
Q2.a (Marks visible) [CLO1, R]: What are the limitations of Programmed I/O?